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? semiconductor components industries, llc, 2012 october, 2012 ? rev. 0 1 publication order number: NCV7471/d NCV7471 system basis chip with a high-speed can, two lins and a boost-buck dc/dc converter NCV7471 is a system basis chip (sbc) integrating functions typically found in automotive electronic control units (ecus) in the body domain. NCV7471 provides and monitors the low ? voltage power supplies for the application microcontroller and other loads, monitors the application software via a watchdog and includes high ? speed can and lin transceivers allowing the ecu to host multiple communication nodes or to act as a gateway unit. the on ? chip state controller ensures safe power ? up sequence and supports low ? power modes with a configurable set of features including wakeup from the communication buses or by a local digital signal wu. the status of several NCV7471 internal blocks can be read by the microcontroller through the serial peripheral interface or can be used to generate an interrupt request. features ? control logic ? ensures safe power ? up sequence and the correct reaction to different supply conditions ? controls mode transitions including the power management and wakeup treatment ? bus wakeups, local wakeups (via wu pin) and cyclic wakeups (through the on ? chip timer) ? generates reset and interrupt requests ? serial peripheral interface ? operates with 16 ? bit frames ? ensures communication with the ecu?s microcontroller unit ? mode settings, chip status feedback and watchdog are accessible through eight twelve ? bits registers ? 5 v vout supply from a dc/dc converter ? can deliver up to 500 ma with accuracy of 2% ? supplies typically the ecu?s microcontroller ? 5 v vout2 low ? drop output regulator ? can supply external loads ? e.g. sensors ? controlled by spi and the state machine ? protected against short to the car battery ? a high ? speed can transceiver ? iso11898 compliant ? txd dominant time ? out protection ? two lin transceivers ? lin2.1 and j2602 compliant ? txd dominant time ? out protection ? wakeup input wu ? edge ? sensitive high ? voltage input ? can be used as a wake ? up source or as a logical input polled through spi ? protection and monitoring functions ? monitoring of the main supply through the v_mid point ? monitoring of vout supply output with programmable threshold ? vout2 supply diagnosis through spi and interrupt ? thermal warning and thermal shutdown protection ? programmable watchdog monitoring the ecu software http://onsemi.com ssop36 ? ep dq suffix case 940ab marking diagram xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx awlyywwg xxxx = specific device code a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package see detailed ordering and shipping information on page 50 of this data sheet. ordering information www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 2 pin connections v_mid boost cfg fso1 fso2 fso3 gnd_smps wu vs vs_vout2 gnd canh canl test/gnd lin1 gnd lin2 swdm 1 18 19 36 rstn intn uvn_vout sdi sck sdo csn buck gnd_sense vout vcc_can vout2 txdc rxdc txdl1 rxdl1 txdl2 rxdl2 table of contents block diagram 3 ............................................................................................... pin description 4 .............................................................................................. application information 5 ....................................................................................... example application diagram 5 .................................................................................. external components 6 .......................................................................................... functional description 7 ......................................................................................... power supplies 7 .............................................................................................. communication transceivers 9 ................................................................................... wu ? local wakeup input 13 .................................................................................... operating modes 14 ............................................................................................ watchdog 18 .................................................................................................. system reset 20 ............................................................................................... event flags and interrupt requests 21 .............................................................................. junction temperature monitoring 24 ............................................................................... fso1/2/3 ? fail-safe outputs 24 .................................................................................. swdm and cfg digital inputs 26 ................................................................................ spi ? serial peripheral interface 26 ................................................................................ absolute maximum ratings 37 ................................................................................... operating ranges 38 ............................................................................................ electrical characteristics 39 ...................................................................................... power supply 39 ............................................................................................... can transceiver 42 ............................................................................................ lin transceivers 44 ............................................................................................ digital control timing and spi timing 46 .......................................................................... thermal protection 47 .......................................................................................... digital io pins 47 .............................................................................................. cfg and swdm pins 48 ........................................................................................ fso pins 48 .................................................................................................. wu pin 48 ................................................................................................... device ordering information 50 ................................................................................... www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 3 figure 1. block diagram can transceiver lin transceiver lin transceiver txdc rxdc txdl1 rxdl1 txdl2 rxdl2 rstn intn sdi sdo sck csn fso fso fso fso1 fso2 fso3 lin1 lin2 canh canl swdm cfg control dc/dc converter vout2 ldo 50 ma vcc_can gnd wu NCV7471 boost gnd_smps vs_vout2 supply monitoring auxiliary blocks vs v_mid buck vout uvn_vout gnd_sense test/gnd www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 4 table 1. pin description pin number pin name pin type (lv = low voltage; hv = high voltage) pin function 1 rstn lv digital input/output; open drain; internal pull ? up system reset 2 intn lv digital output; open drain; internal pull ? up interrupt request to the mcu 3 uvn_vout vout under ? voltage signal to the mcu 4 sdi lv digital input; internal pull ? down spi data input 5 sck lv digital input; internal pull ? down spi clock input 6 sdo lv digital output; push ? pull with tri ? state spi data output 7 csn lv digital input (hv tolerant); internal pull ? up spi chip select input 8 buck hv analog input/output connection of l buck coil to the integrated serial switch 9 gnd_sense ground connection ground sense for the internal circuitry (e.g. vout2 regulator) 10 vout lv supply input feedback of the dc/dc converter output; main 5 v lv supply for the digital io?s 11 vcc_can lv supply input core supply for the can transceiver 12 vout2 lv supply output output of the 5 v/50 ma low ? drop regulator for external loads 13 txdc lv digital input; internal pull ? up input of the data to be transmitted on can bus 14 rxdc lv digital output; push ? pull output of data received from can bus 15 txdl1 lv digital input; internal pull ? up input of the data to be transmitted from lin1 bus 16 rxdl1 lv digital output; push ? pull output of data received on lin1 bus 17 txdl2 lv digital input; internal pull ? up input of the data to be transmitted from lin2 bus 18 rxdl2 lv digital output; push ? pull output of data received on lin2 bus 19 swdm hv digital input; internal pull ? down input to select the sw development configuration 20 lin2 lin bus interface lin2 bus line 21 gnd ground connection ground connection 22 lin1 lin bus interface lin1 bus line 23 test/gnd lv digital input; internal pull ? down test ? mode entry pin for production testing; should be grounded in the application 24 canl can bus interface canl line of the can bus 25 canh can bus interface canh line of the can bus 26 gnd ground connection ground connection 27 vs_vout2 hv supply input separate line input for the vout2 low ? drop regulator 28 vs hv supply input line supply for the battery ? related core blocks 29 wu hv digital input input for monitoring of external contacts 30 gnd_smps ground connection power ground connection for the dc/dc converter 31 fso3 hv digital output; open drain low ? side indication of a fail ? safe event by rectangular signal of 100 hz with 20% duty cycle; high ? impedant in normal operation 32 fso2 hv digital output; open drain low ? side indication of a fail ? safe event by rectangular signal of 1.25 hz with 50% duty cycle; high ? impedant in normal operation 33 fso1 hv digital output; open drain low ? side indication of a fail ? safe event by static low level; high ? impedant in normal operation 34 cfg hv digital input; internal pull ? down configuration of fail ? safe behavior; in sw development, cfg enables boost stage operation 35 boost hv analog input/output connection of l boost coil to the integrated switch to ground. 36 v_mid hv analog input/output intermediate point connecting the step ? up and step ? down stages of the dc/dc converter www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 5 application information figure 2. example application diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 6 external components overview of external components from application schematic in figure 2 is given in table 2 together with their recommended or required values. table 2. external components overview component name description value note d rev reverse ? protection diode parameters application ? specific; e.g. 0.5 a / 50 v values and types depend on the application needs and conditions. guidelines for their selection can be found in the product?s application note. the given examples are suitable for vout loads of up to 250 ma, and for v_in above 3.3 v. c in filtering capacitor for the dc/dc converter input 1 f ceramic; e.g. 1 f / 40 v l boost inductor for the converter boost stage; emc filtering inductance recommended range 3.3 h ? 10 h; e.g. 3.3 h / 0.77 a, type b82422h1332+000 d 1 diode for the converter boost stage shottky or ultra ? fast; parameters application ? specific; e.g. 0.5 a / 50 v c mid filtering and stabilization capacitor for the converter intermediate voltage 1 f ceramic; e.g. 1 f / 40 v d 2 diode for the converter buck stage shottky or ultra ? fast; parameters application ? specific; e.g. 0.25 a / 50 v l buck inductor for the converter buck stage recommended range 10 h ? 22 h; e.g. 10 h / 0.5 a, type b82422h1103+000 c out filtering and stabilization capacitor for the converter output voltage 10 f ceramic; e.g. 10 f / 10 v c vs filtering capacitor for the vs input supplying lin and auxiliary internal circuitry recommended >100 nf ceramic optional; depends on the application pcb c in2 filtering capacitor for the vout2 regulator input recommended >100 nf ceramic optional; depends on the application pcb c out2 filtering and stabilization capacitor for the vout2 regulator output >1 f ceramic (recommended 2.2 f nominal) required for vout2 stability r wu protection and filtering resistor for the wu input recommended 33 k nominal optional; depends on the application needs r fso depends on the application needs d pu_lin pull ? up diode on lin line required only for master lin node r pu_lin pull ? up resistor on lin line 1 k nominal c lin filtering capacitor on lin line typically 100 pf ? 220 pf nominal optional; is function of the entire lin network c vcc_can filtering capacitor on the can transceiver supply input recommended >100 nf ceramic optional; depends on the application pcb can termination and protection optional; is function of the entire can network r pu_dig pull ? up resistor for the open ? drain digital outputs (intn, rstn, uvn_vout) recommended 10 k nominal optional; only if the integrated pull ? ups are not sufficient for the application r swdm protection resistor on swdm input recommended 10 k nominal optional; depends on the application r cfg protection resistor on cfg input recommended 10 k nominal optional; depends on the application cfg connection details can be found in the product?s application note. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 7 functional description power supplies vs supply input vs pin of NCV7471 is typically connected to the car battery through a reverse ? protection diode and can be exposed to all relevant automotive disturbances (iso7637 pulses, system esd...). vs supplies mainly the integrated lin transceivers. filtering capacitors should be connected between vs and gnd. v_mid supply point v_mid node is the connection point between the two stages of the dc/dc converter. if only the buck (i.e. step ? down) function of the converter is active (because the input voltage is sufficient or because boosting is not enabled), v_mid level stays two diode drops below the battery input to the application ? see figure 2. in case the boost stage of the converter is active, v_mid voltage is regulated to v_mid_reg (6.5 v typically). v_mid pin is used to supply the core auxiliary blocks of the device ? namely the voltage reference, biasing, internal regulator and the wakeup detector of the can bus. when the dc/dc converter is boosting, it is ensured that the internal core blocks remain functional even for low input supply level. during power ? up of the battery supply, v_mid point must reach v_mid_porh level in order for the circuit to become functional ? the internal state machine is initiated and the converter is activated in buck ? only mode. the circuit remains functional until v_mid falls back below v_mid_porl level, when the device enters the shut ? down mode. vout dc/dc converter the main application low ? voltage supply is provided by an integrated boost ? buck dc/dc converter, delivering a 5 v output vout. the converter can work in two modes: ? buck ? only mode is the default mode of the vout power ? supply. in this mode, the boosting part of the converter is never activated and the resulting vout voltage can be only lower than the input line voltage. buck ? only mode is applied during the initial power ? up (after the v_in connection), wakeup from sleep ? mode and also recovery from the fail ? safe mode. ? boost ? buck mode ensures that the correct vout voltage is generated even if the input line voltage falls below the required vout level. this mode can be requested through the corresponding spi control register. if selected, the boost ? buck mode is used during reset, start ? up, normal, standby, and flash modes. it is also preserved during vout under ? voltage recovery through power ? up mode. in sw development configuration, boost ? buck mode can be additionally enabled by high level on cfg pin. no spi communication is therefore necessary to select the dc/dc mode in sw development ? see table 3. table 3. control of dc/dc converter modes (?x? means ?don?t care?) device configuration spi enboost bit signal on cfg pin applied dc/dc mode config 1, 2, 3, 4 low x buck ? only high boost ? buck sw development low low buck ? only high boost ? buck high x boost ? buck by default, the converter works with a fixed switching frequency fsw_dcdc (typ. 485 khz). through the spi settings, a switching frequency modulation can be applied with fixed modulation frequency of 10 khz and three selectable modulation depth values ? 10%, 20% or 30% of the nominal frequency. vout level is monitored by an under ? voltage detector with multiple thresholds: ? comparison with selectable threshold vout_resx . by default, the lowest threshold (typ. 3.1 v) applies for the state machine control and the activation of the rstn signal. this reset threshold can be changed via spi to any of the four programmable values. ? a second monitoring signal ? uvn_vout ? is generated based on comparison of the vout level with the highest monitoring level (typ. 4.65 v). ? vout is compared with a fixed threshold vout_fail (typ. 2 v). if vout stays below vout_fail level for longer than t_vout_powerup during the power ? up mode, a vout short ? circuit is detected and fail ? safe mode is entered with the corresponding fail ? safe information stored in spi. both uvn_vout and rstn pins provide an open drain output with integrated pull ? up resistor. the split between reset ? generating level vout_resx and an under ? voltage indication allows coping with vout dips in case of high loads coinciding with low input line voltages. the function of the vout and v_mid monitoring is illustrated in figure 3 and figure 4. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 8 figure 3. v_mid and vout supply monitoring (filtering times are neglected) figure 4. vout monitoring www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 9 vout2 auxiliary supply an integrated low ? drop regulator provides a second 5 v supply vout2 to external loads, typically sensors. the regulator?s input is taken from a dedicated pin vs_vout2, which does not feature an explicit under ? voltage monitoring. vs_vout2 would be typically connected to the vs pin or, in function of the application needs, might be taken from other nodes like, e.g., the dc/dc converter?s auxiliary node v_mid. after a power ? up or a reset event, as well as in sleep mode, vout2 regulator is switched off. in start ? up, normal, standby and flash modes, it can be freely activated or deactivated via spi control register. vout2 is diagnosed for under ? voltage and over ? voltage via comparators with fixed thresholds vout2_uv and vout2_ov , respectively. under ? voltage detection is working only when vout2 regulator is on, while the over ? voltage is monitored regardless the vout2 regulator activation. output of both detectors can be polled via spi status bits. change of the detection status (in either direction) is recorded as an spi flag bit and, if enabled, can lead to an interrupt. vcc_can transceiver supply the integrated can transceiver uses a dedicated supply input vcc_can. the transceiver is supplied by vcc_can when conf igured for full ? speed transmission or reception. when configured for wakeup detection, the transceiver is internally supplied from the v_mid pin. a 5 v supply must be externally connected to vcc_can pin for the correct transceiver ?s functionality in full ? speed mode (?can normal? or ?can receive ? only?). vcc_can input has no dedicated monitoring and its correct level shall be ensured by the application ? e.g. if vout is connected to vcc_can, then vout under ? voltage monitoring can also cover the correct vcc_can level. communication transceivers high ? speed can transceiver NCV7471 contains a high ? speed can transceiver compliant with iso11898 ? 2 and iso11898 ? 5 standards, consisting of a transmitter, receiver and wakeup detector. the can transceiver can be connected to the bus line via a pair of pins canh and canl, and to the digital control through pins txdc and rxdc. the functional mode of the can transceiver depends on the chip operating mode and on the status of the corresponding spi bits ? see t able 4, t able 5 and figure 5. table 4. can transceiver spi control spi control bits can transceiver function in operating modes modcan.1 modcan.0 power ? up reset start ? up normal flash standby sleep fail ? safe (except thermal shut ? down) 0 0 can off can off can off can off can wakeup 0 1 can off can wakeup can wakeup can wakeup can wakeup 1 0 can off can receive ? only can receive ? only can off can wakeup 1 1 can off can normal can off can off can wakeup table 5. can transceiver modes mode transceiver rxdc pin txdc pin canh/canl pins supply can off fully off high (if vout available) ignored biased to gnd n.a. can wakeup wakeup detector active low if wakeup detected; high otherwise (if vout available) ignored biased to gnd v_mid can receive ? only receiver active received data ignored biased to vcc_can/2 vcc_can can normal transmitter and receiver active received data data to transmit; checked for time ? out biased to vcc_can/2 vcc_can www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 10 figure 5. can transceiver modes can off can wake ? up can receive ? only can normal can mode canh/canl txdc rxdc t_txdc_timeout v_mid can supply vcc_can bias of bus pins to gnd to vcc_can/2 can wakeup detected wakeup flag read & cleared in can off mode, the can transceiver is fully deactivated. pin rxdc stays high (as long as vout is provided) and logical level on txdc is ignored. the bus pins are weakly biased to ground via the input impedance. in can wakeup mode, the can transceiver, being supplied purely from v_mid pin, detects wakeups on the can lines. a valid wakeup on the can bus corresponds to a pattern of two dominants at least t_can_wake_dom long, interleaved by a recessive at least t_can_wake_rec long. the total length of the pattern may not exceed t_can_wake_timeout. the can wakeup handling is illustrated in figure 6. in function of the current operating mode, a can wakeup can lead either to an interrupt request or to a reset. a can wakeup is also indicated by a low level on the rxdc pin (which otherwise stays high as long as vout is available). logical level on txdc pin is ignored. the bus pins remain weakly biased to ground in the wakeup can mode. figure 6. can wakeup detection < t_can_wake_dom > t_can_wake_dom > t_can_wake_dom > t_can_wake_rec < t_can_wake_timeout canh/canl rxdc dominant too short rstn intn can wakeup detected wakeup flag read&cleared via spi intn wakeup from sleep mode wakeup in start ? up, normal, standby, flash www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 11 in can receive ? only mode, the receiver part of the can block detects data on the bus with the full speed and signals them on the rxdc pin. logical level on txdc pin is ignored. the receiver is supplied from the vcc_can supply input. the bus pins are biased to vcc_can/2 level through the input circuitry. in can normal mode, the full can transceiver functionality is available. both reception and transmission at the full speed can be used. received data are signaled via rxdc pin, while logical level on txdc pin is translated into the corresponding bus level (txdc = high or low leading to a recessive or dominant being transmitted, respectively). both the receiving and the transmitting part are supplied from the vcc_can supply input. the bus pins are biased to vcc_can/2 level through the input circuitry. txdc input signal is monitored with a time ? out timer. if a dominant longer than t_txdc_timeout is requested (i.e. txdc is low for longer than t_txdc_timeout ), the transmission is internally disabled. the reception from the can bus remains functional and the internally set can transceiver mode does not change. the transmission is again enabled when txdc becomes high. lin transceivers NCV7471 integrates two on ? chip lin transceivers ? interfaces between physical lin buses and the lin protocol controllers compatible to lin2.1 and j2602 specifications ? consisting of a transmitter, receiver and wakeup detector. each lin transceiver can be connected to the bus line via linx pin, and to the digital control through pins txdlx and rxdlx. the functional mode of the lin transceivers depends on the chip operating mode and on the status of the corresponding spi bits ? see table 6, table 7, and figure 7. the lin transceivers are supplied directly from the vs pin. table 6. lin transceivers spi control spi control bits x = 1 ... 2 linx transceiver function in operating modes modlinx.1 modlinx.0 power ? up reset start ? up normal flash standby sleep fail ? safe (except thermal shut ? down) 0 0 linx off linx off linx off linx off linx wakeup 0 1 linx off linx wakeup linx wakeup linx wakeup linx wakeup 1 0 linx off linx receive ? only linx receive ? only linx off linx wakeup 1 1 linx off linx normal linx normal linx off linx wakeup table 7. lin transceivers modes mode transceiver rxdlx pin txdlx pin linx pin bias linx off fully off high (if vout available) ignored pull ? up current source to vs linx wakeup wakeup detector active low if wakeup detected; high otherwise (if vout available) ignored pull ? up current source to vs linx receive ? only receiver active received data ignored pull ? up current source to vs linx normal transmitter and receiver active received data data to transmit; checked for time ? out (if enabled via spi); transmitted if vs> vs_mon 30 k pull ? up www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 12 figure 7. lin transceiver modes linx off linx wake ? up linx receive ? only linx normal linx mode linx txdlx rxdlx t_txdl_timeout bus pin pull ? up current source lin wakeup detected recessive dominant wakeup flag read & cleared 30 k resistor if txdl time ? out disabled in linx off mode, the respective lin transceiver is fully deactivated. pin rxdlx stays high (as long as vout is provided) and logical level on txdlx is ignored. the bus pin is internally pulled to vs with a current source (thus limiting vs consumption in case of a permanent linx short to gnd). in linx wakeup mode, the lin transceiver detects wakeups on the lin line. a valid wakeup on the lin bus corresponds to a dominant at least t_lin_wake long, followed by a recessive. thus the wakeup will not be detected in case of a permanent lin short to gnd, because a rising edge on lin is necessary for the wakeup detection ? see figure 8. in function of the current operating mode, a lin wakeup can lead to an interrupt request or to a reset. a lin wakeup is also indicated by a low level on the corresponding rxdlx pin (which otherwise stays high as long as vout is available). logical level on txdlx pin is ignored; bus pin is internally pulled to vs with a current source. figure 8. lin wakeup detection < t_lin_wake linx recessive dominant t_lin_wake lin wakeup detected wakeup flag read&cleared via spi rxdlx rstn intn intn wakeup from sleep mode wakeup in start ? up, normal, standby, flash www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 13 in linx receive ? only mode, the receiver part of the linx block detects data on the bus with the normal speed and signals them on the rxdlx pin. logical level on txdlx pin is ignored; bus pin is internally pulled to vs with a current source. in linx normal mode, the full lin transceiver functionality is available. both reception and transmission at the normal speed can be used. received data are signaled via rxdlx pin, while logical level on txdlx pin is translated into the corresponding bus level (txdlx = high or low leading to a recessive or dominant being transmitted, respectively). the linx pin is internally pulled to vs via a 30 k resistive path. txdlx input signal is monitored with a time ? out timer. if a dominant longer than t_txdl_timeout is requested (i.e. txdlx is low for longer than t_txdl_timeout ), the transmission is internally disabled. the reception from the linx bus remains functional and the internally set linx transceiver mode does not change. the transmission is again enabled when txdlx becomes high. the txdl dominant time ? out feature can be disabled via spi (a common setting for both lin blocks). transmission onto the bus is blocked if vs supply falls below vs_mon level. vs monitoring does not influence the lin reception or the txdlx time ? out detection. indication of the vs monitoring is accessible through spi bit statvs_low . for applications with lower required bit rates, the transmitted lin signal slope can be decreased by a dedicated spi setting (?lin low ? slope mode?). wu ? local wakeup input wu pin is a high ? voltage input typically used to monitor an external contact or switch. a stable logical level of the wu signal is ensured even without an external connection: ? if the wu level is high for longer than t_wu_filt , an internal pull ? up current source is connected to wu ? if the wu level stays low for longer than t_wu_filt , an internal pull ? down current source is connected to wu the logical level on pin wu can be polled through spi or used as a wakeup source: ? wu signal polling : in start ? up, normal, standby and flash modes, the current wu logical level is directly reflected in spi bit statwu , available for readout ? wu edge detection / wake ? up : by setting spi bits modwu.1 and modwu.0 , edge detection is applied to wu signal. the device can be set to detect rising, falling or both edges on the wu signal. when the selected edge is detected, the event is latched in spi bit flagwakewu . in function of the current operating mode, edge on wu leads to an interrupt request (start ? up, normal, standby and flash modes) or reset (sleep mode). more details on the event handling, applicable also to wu edges, are given in the event flags and interrupt requests section. handling of the wu pin signal is illustrated in figure 9. figure 9. wu pin handling wu t_wu_filt t_wu_filt < t_wu_filt < t_wu_filt vth_wu (with hystheresis) pull ? up current pull ? down current pull ? up current t_wu_del t_wu_del internal wu connection wu falling edge detected wu rising edge detected spi read ? out (if available) www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 14 operating modes the principal operating modes of NCV7471 are shown in figure 10 and described in the following paragraphs. figure 10. operating modes missed watchdog rstn pin forced low any mode fail ? safe ? vout: off ? vout2: off ? watchdog: off ? rstn: low ? uvn_vout: low ? spi: off ? can, linx, wu: wake ? up (except thermal shutdown) power ? up ? vout: on ? vout2: off ? watchdog: off ? rstn: low ? uvn_vout: low (=uv indication) ? spi: off ? can, linx: off reset start timer t_vout_reset ? vout: on ? vout2: off ? watchdog: off ? rstn: low ? uvn_vout: uv indication ? spi: off ? can, linx: off start ? up ? vout: on ? vout2: per spi ? watchdog: time ? out ? rstn: high ? uvn_vout: uv indication ? spi: on ? can, linx: per spi (normal in swd configuration) normal ? vout: on ? vout2: per spi ? watchdog: window/time ? out ? rstn: high ? uvn_vout: uv indication ? spi: on ? can, linx: per spi standby ? vout: on ? vout2: per spi ? watchdog: time ? out/off/cyclic wake ? rstn: high ? uvn_vout: uv indication ? spi: on ? can, linx: per spi sleep ? vout: off ? vout2: off ? watchdog: off ? rstn: low ? uvn_vout: low ? spi: off ? can, linx: per spi flash ? vout: on ? vout2: per spi ? watchdog: time ? out ? rstn: high ? uvn_vout: uv indication ? spi: on ? can, linx: per spi shut ? down ? vout: off ? vout2: off ? watchdog: off ? rstn: low ? uvn_vout: low ? spi: off ? can, linx: off any mode with vout active v_mid < v_mid_porl v_mid > v_mid_porh vout > vout_resx spi vout < vout_resx spi wake ? up wd service ok (if enabled) failure event t_vout_reset elapsed configuration ? read and store swdmn pin state ? read and store cfg pin state ? vout: off spi wd service ok wake ? up or thermal shut ? down recovery spi spi wd service ok reset mode requested wrong mode request flash mode spi request after flash spi request normal mode spi request www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 15 shut ? down mode the shut ? down mode is a passive state, in which all NCV7471 resources are inactive. the shut ? down mode provides a defined starting point for the circuit in case of supply under ? voltage or the first supply connection. both on ? chip power ? supplies ? vout and vout2 ? are switched off and the can/linx transceiver pins (canh, canl and linx) remain passive so that they do not disturb the communication of other nodes connected to the buses. no wakeups can be detected. the spi interface is disabled (sdo pin remains high ? impedant). pins rstn and uvn_vout are forced low ? rstn/uvn_vout low level is guaranteed, when v_mid supply is above v_mid_digout_low or vout pin is above vout_digout_low . pins rxdx are kept high (i.e. at vout level). the shut ? down mode is entered asynchronously whenever the v_mid level falls below the power ? on ? reset level v_mid_porl . the shut ? down mode is left only when the v_mid supply exceeds the high power ? on ? reset level v_mid_porh . when exiting the shut ? down mode, NCV7471 always enters the configuration mode. configuration mode configuration is a transient mode, in which NCV7471 reads logical input levels on pins swdm and cfg. the swdm and cfg values in configuration mode define watchdog and fail ? safe behavior of the chip, respectively. after leaving the configuration mode, the device configuration can be changed neither by the spi communication nor by signal modifications on the swdm and cfg pins and is kept until the next v_mid under ? voltage. the application software can also force configuration mode by an spi request from start ? up or normal mode. table 8 summarizes the available configurations and their characteristics. after reading both pins? levels, NCV7471 automatically transitions into the power ? up mode. because the smps is off in configuration mode, spi ? initiated transition from a functional mode to configuration may result in a short dip on vout, which is not disturbing the device operation and which is recovered immediately after the configuration mode is left. cfg pin connection details can be found in the product?s application note. two spi bits are foreseen to reflect the state of swdm and cfg pins: ? statswdm bit latches the swdm pin logical value read during configuration mode. the bit remains unchanged until the configuration mode is entered again. ? statcfg bit either latches the cfg value read in configuration mode and remains unchanged afterwards (in config 1,2,3,4), or keeps reflecting the current cfg signal throughout the ic operation (in sw development). table 8. possible configurations (?x? means ?don?t care?) fastfson spi bit values latched in configuration mode resulting configuration behavior swdm cfg at watchdog failure at rstn clamped low 1 0 1 config 1 1 st failure activates fsox; fail ? safe mode not entered fsox activated; external reset controls the operating mode 1 0 0 config 2 1 st failure puts the chip into fail ? safe mode fsox activated; fail ? safe mode entered 0 0 1 config 3 2 nd failure activates fsox; fail ? safe mode not entered fsox activated; external reset controls the operating mode 0 0 0 config 4 2 nd failure activates fsox and puts the chip into fail ? safe mode fsox activated; fail ? safe mode entered x 1 x sw development no fsox activation; no fail ? safe mode entry; stored in spi, can lead to interrupt (if enabled) external reset controls the operating mode; no fsox activation power ? up mode the power ? up mode ensures correct activation of the on ? chip vout dc/dc converter or recovery of vout after an under ? voltage event. in the power ? up mode, the vout dc/dc converter is switched on (or kept on) while vout2 regulator remains in the previous state (e.g. vout2 is off coming from the shut ? down and configuration modes). the can/linx transceiver pins (canh, canl and linx) remain passive so that they do not disturb the communication of other nodes connected to the buses. no wakeups can be detected. the spi interface is disabled (sdo pin remains high ? impedant). pins rstn and uvn_vout are forced low. pins rxdx are kept high (i.e. at vout level). the power ? up mode is entered from the configuration mode or after a wakeup from sleep mode (in both cases, vout dc/dc converter needs to be activated). it will be also entered from any state with vout already active (normal, standby, reset, start ? up, flash) if the vout level falls below the vout_resx level (the valid vout_resx level is set via spi). www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 16 the power ? up mode is correctly left when vout exceeds the spi ? selected vout_resx level. an overload/short ? circuit failure is detected if vout does not reach the failure threshold vout_fail within time t_vout_powerup . NCV7471 then goes to the fail ? safe mode. vout staying between vout_fail and vout_resx levels will keep the device in the power ? up mode, unless the thermal shutdown temperature is reached (e.g. because of vout overload). reset mode the reset mode is a transient mode providing a defined rstn pulse for the application microcontroller. vout supply is kept on, while vout2 regulator remains in its previous state. the can/linx transceiver pins (canh, canl and linx) are passive so that they do not disturb the communication of other nodes connected to the buses. no wakeups can be detected. the spi interface is disabled (sdo pin remains high ? impedant). pin rstn is forced low while pin uvn_vout indicates the vout under ? voltage with respect to the highest reset level. pins rxdx are kept high (i.e. at vout level). reset mode will be entered as a consequence of one of the following events: ? power ? up mode is exited ? rstn pin is forced low externally ? flash mode has been requested via spi ? flash mode exit has been requested via spi ? reset mode has been requested via spi ? an un ? authorized operating mode has been requested via spi ? watchdog has been missed in config 1 or config 3 normally, the reset mode is left after a defined time t_vout_reset when the rstn pin is internally released to high ? the chip then goes to the start ? up mode. overdriving the rstn pin to low externally will extend the reset mode duration. if rstn is still forced low externally even after time t_vout_clamped_low elapses, a ?rstn clamped low? event is detected. the reaction depends on the chip configuration (sw development or config 1/2/3/4). ?rstn clamped low? can lead to fsox signal activation, fail ? safe mode entry or just to the reset mode being kept as long as rstn is driven low ? see table 9. if the reset mode is entered due to external rstn low pulse during start ? up mode, fsox outputs are activated (unless the device is in the sw development configuration). this condition fosters that the external mcu sends at least one correct watchdog message before applying an external reset. information about the cause of a reset pulse is stored in the spi registers and can be read by the application software. the ?reset source? information is kept unchanged until the next reset event. start ? up mode during the start ? up mode, the microcontroller supplied by vout is expected to initialize correctly and to perform successful communication via the spi interface. start ? up mode is the first mode in which spi is enabled and the watchdog is started. the application software is able to read any spi register. write access to spi depends on the fso_internal flag (i.e. whether a failure condition preceded the start ? up mode ? see the fso1/2/3 ? fail ? safe outputs section for details): ? in case fso_internal = 0 (inactive), any spi register can be written and all features can be configured in the start ? up mode (e.g. can/lin transceivers can be activated, vout2 can be activated) ? in case fso_internal = 1 (active), all spi write frames will be ignored by the chip, with the exception of the watchdog service frame (write access to the mode_control register). the watchdog is activated and works in the timeout mode. a correct watchdog service is expected from the mcu before the watchdog period elapses. the correct watchdog ? serving spi message should arrive in time and should contain either a request to enter normal mode or a request to enter the flash mode. the start ? up mode is then exited into the requested mode. if the microcontroller software fails to serve the watchdog in time, the chip detects the ?1 st watchdog missed? event which is handled according the configuration (sw development or config 1/2/3/4) ? see the fso1/2/3 ? fail ? safe outputs section. in the sw development configuration, the following exceptions are applied for the start ? up mode: ? the device remains in the start ? up mode as long as the watchdog is not served correctly ? thus also in case no microprocessor is connected. ? when entering the start ? up mode, can and both lin transceivers are automatically put to their normal mode as a result, device in sw development mode keeps on providing vout supply and full can and lin functionality even if no application software is available or if no microprocessor is connected. in addition, no rstn pulses are generated and fsox pins remain inactive. normal mode the normal mode allows using all NCV7471 resources (vout2, can transceiver, linx transceivers) which can be monitored and configured by the microcontroller via the spi interface. the watchdog is working in the window mode with selectable period which can be changed at each watchdog ? service spi message. vout is kept on. intn pin provides the interrupt requests (irq?s) depending on the device status and the interrupt mask settings. the application software can poll all www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 17 spi status bits or enable the corresponding interrupt requests. pin rstn remains high while pin uvn_vout indicates the vout under ? voltage with respect to the highest reset level. wu pin and transceivers can be configured for wake ? up recognition which is then signalled as an interrupt request. in a software ? controlled way, the microcontroller can either keep NCV7471 in the normal mode or request a transition into another mode (including reset and configuration). standby mode standby is the first low ? power mode of NCV7471. it is entered after the corresponding spi request is made in the normal mode. in the standby mode, the application microcontroller remains supplied by vout dc/dc converter and can continue the spi communication. vout remains monitored by the reset and failure comparators. the functionality of the linx blocks remains fully available while the can transceiver is limited ? it can be put to receive ? only, wakeup or off mode. active can transmission is not available. three types of wakeup can be used during the standby mode ? a local wakeup through the wu pin change, a bus wakeup (via a can or linx bus) and a cyclic wakeup generated by the watchdog timer. a detected wakeup will cause an interrupt request through intn pin. during standby mode, at least one of the following conditions must be fulfilled: ? watchdog is requested to be on ? cyclic wakeup is enabled ? can wakeup is enabled ? lin wakeup is enabled at least on one of the linx channels if none of the above conditions is respected, all can and lin wakeups will be automatically enabled as well as wu wakeup on both edges. note, that allowing only the local wu wakeup is not sufficient for successful standby mode entry without watchdog. this spi setting condition is monitored and fostered throughout the standby mode duration. standby will be kept as long as the microcontroller can correctly serve the watchdog and the interrupts according the spi settings. standby is left either by an spi request for a mode change or by a reset event. sleep mode sleep mode is the second low ? power mode of NCV7471. the microcontroller is not supplied and most resources are inactive beside the blocks needed for wakeup detection. sleep mode can be entered from normal mode by the corresponding spi request. immediately after the sleep mode entry, rstn and uvn_vout pins are pulled low in order to stop the microcontroller software. both power supplies ? vout and vout2 ? are switched off; spi and watchdog are de ? activated. depending on the spi settings prior to the sleep mode entry, can and linx transceivers can be either switched off or configured for bus wakeup detection. two types of wakeup can be used during the sleep mode ? a local wakeup through the wu pin change, and a bus wakeup (via a can or linx bus). a detected wakeup will cause entry into power ? up mode. when sleep mode is requested, at least one of the following conditions must be fulfilled: ? can wakeup is enabled ? lin wakeup is enabled at least on one of the linx channels if none of the above conditions is respected, all can and lin wakeups will be automatically enabled as well as wu wakeup on both edges. note, that allowing only the local wu wakeup is not sufficient. sleep mode can be only left through a wakeup or v_mid under ? voltage. fail ? safe mode fail ? safe mode ensures a defined reaction of NCV7471 to a failure event. both power supplies ? vout and vout2 ? are switched off, and the fail ? safe outputs are activated. rstn and uvn_vout pins are pulled low in order to ensure that the microcontroller software execution stops immediately. fail ? safe mode will be entered as a consequence of one of the following events: ? watchdog has been missed in config 2 or config 4 ? ?rstn clamped low? has been detected in config 2 or config 4 ? ?rstn clamped high? has been detected ? vout power supply has not reached the failure level vout_fail after t_vout_powerup ? this situation can be encountered during failed chip start ? up or during too long and deep under ? voltage ? fail ? safe mode has been requested via spi (in sw development only) ? thermal shut ? down has been encountered all can and linx transceivers are automatically configured to wakeup detection; wakeup from wu pin is also enabled on both edges. a detected bus or wu wakeup will bring NCV7471 into power ? up mode. only in case of a thermal shut ? down, no wakeups are detected and the fail ? safe mode is exited as soon as the junction temperature decreases below the warning level. throughout the fail ? safe mode, some spi settings and status bits are preserved, and become effective after fail ? safe mode recovery. namely control2 register (with smps mode settings and vout reset level settings), status1 register (with wake ? up flags and fso flags) and general purpose register are not reset when fail ? safe is entered, and keep their previous content. fail ? safe www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 18 recovery is therefore different compared to wakeup from sleep mode, after which control2 is reset. flash mode flash mode offers a relaxed watchdog timing enabling transfer of bigger amounts of data between the microcontroller software and, e.g., an external programmer connected to a can or lin bus. the watchdog is running in time ? out mode and its period can be selected from the full range of available values including longer times compared to normal mode. the control of other resources ? power supplies, transceivers, wu pin, interrupt requests, etc. ? remains identical to normal mode. flash mode can be entered by a specific spi request in start ? up or normal mode. the entry into flash is accompanied by a reset pulse with ?flash requested? flag. similarly, flash mode can be left by an spi request which will result in a reset pulse with ?flash exit requested? flag. reset ? source information in the spi flags then allows the application to branch in function of the flash mode. the handling of flash mode requests is shown in figure 11. in sw development configuration, can and both lin transceivers are automatically put to their normal mode when the device enters flash operating mode. figure 11. flash mode sequence start ? up/normal operating mode spi mode request reset source flag in spi flash rstn flash flash flash reset flash flash flash flash normal reset start ? up normal normal xxxxx flash mode requested flash mode exited opmode spi read ? back start ? up/normal flash start ? up normal n/a n/a watchdog the NCV7471 watchdog timer monitors the correct function of the application software ? the microcontroller is required to send correct and timely watchdog ? service (or ?wd trigger?) spi messages. a failure in the watchdog service is handled in function of the chip?s configuration (see the configuration mode section): it leads to a reset, to the fail ? safe mode entry or ? in the sw development configuration ? generates an interrupt event (maskable). the available modes of the watchdog timer are shown in figure 12, with the watchdog period specified in figure 13: ? time ? out mode watchdog: the microcontroller is expected to send the watchdog ? service spi message any time before the watchdog period elapses. the time ? out watchdog mode is automatically used during start ? up and flash modes. it can be used in standby and normal modes. in standby and flash modes, the watchdog period can be selected from a broader range of values compared to the normal mode. ? window mode watchdog: the microcontroller must send the required spi message during an ?open window? ? this window is situated between 50% and 100% of the watchdog period. a watchdog ? service spi message sent before or after the open window is treated as a watchdog failure. the window watchdog can be used during the normal mode. ? off: the watchdog will be inactive by default in shut ? down, configuration, power ? up, reset, and fail ? safe modes. it can be requested to be off in the standby mode. ? timer wakeup: in the standby mode, the watchdog timer can be configured to generate wakeup events. in the standby mode an interrupt request will be generated with a period defined by the watchdog setting. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 19 figure 12. watchdog modes start ? up mode time ? out watchdog default period used normal mode window or time ? out watchdog period can be changed at every watchdog service flash mode time ? out watchdog period can be changed at every watchdog service watchdog off watchdog timer stopped; spi period definition ignored in standby; spi blocked in sleep time ? out watchdog period fixed @ spi period definition timer wakeup watchdog used to through intn; spi period definition reset mode spi correct wd service spi spi spi correct wd service cyclic irq watchdog off watchdog timer stopped; spi period definition spi blocked in sleep standby mode sleep mode failed wd service (*) or spi request spi failed wd service (*) (*) exact handling of a failed watchdog service depends on the configuration wakeup mode entry; ignored generated wakeup ignored ignored in sleep; after flash spi request flash mode spi request a watchdog ? service corresponds to a write access to spi control0 register, containing watchdog mode, watchdog period and operating mode settings. the csn rising edge of the control0 spi write access is considered as the watchdog trigger moment. the watchdog service is evaluated as successful if all below conditions are fulfilled: ? the write spi frame is valid ? the watchdog trigger moment falls into the correct watchdog trigger interval (see figure 13) ? in the case of the time ? out watchdog, it arrives before the watchdog period expires; in the case of the window watchdog, it arrives during the second half of the window interval. in both cases, tolerance of the watchdog timing parameters shall be taken into account. ? the requested watchdog mode and the requested operating mode form an allowed combination the watchdog period value written during a successful watchdog service is immediately used during the subsequent operation. in the sw development configuration, a failed watchdog service does not lead either to reset or to fail ? safe mode: ? a failed wd service event is stored into the corresponding spi register ? if the event is not masked, an interrupt request is generated. ? if a time ? out watchdog is missed in the start ? up operating mode, start ? up mode is kept, and the watchdog is restarted with the default time ? out period. ? if a too early window wd service is encountered in the normal mode, a new watchdog period will be immediately started with the newly written settings; normal mode is preserved ? if a window ? watchdog is missed in the normal mode (no service arrives), a new watchdog period will be immediately started with the current settings; normal mode is preserved ? if a time ? out watchdog is missed in the standby mode, a new time ? out watchdog period is immediately started with the same period; standby mode is preserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 20 figure 13. structure of the time ? out and window watchdog period safe trigger of time ? out wd reset or previous wd service nominal t_wd_tox t_wd_tox tolerance time ? out safe trigger of window wd 50% of nominal t_wd_winx t_wd_winx tolerance window wd period nominal t_wd_winx 50% of t_wd_winx tolerance previous wd service closed window (wd trigger would be too early) t_wd_winx_trig recommended wd trigger wd expired wd period system reset a reset to the application microcontroller is signaled by low level on the rstn pin. rstn pin is a bidirectional digital pin using an open ? drain output structure with an internal pull ? up resistor. an external reset source can overrule the high level generated by NCV7471 on rstn pin. the rstn logical level is then a superposition of the internally and externally driven reset request. the rstn pin level is compared with the internally driven rstn signal ? the comparison is used to control the operating mode of the circuit and to monitor a clamped condition of the rstn pin ? see table 9. with the exception of the sw development configuration, applying an external reset during the start ? up mode will result in the fso outputs activation. this condition fosters that the external mcu sends at least one correct watchdog message before applying an external reset. table 9. rstn pin function (?x? means ?don?t care?) rstn configuration mode action internally driven sensed at the pin rstn pin follows internal drive low low x x follow normal state diagram high high x x follow normal state diagram rstn pin clamped high low high x configuration, power ? up, reset, sleep go to fail ? safe after t_rstn_clampedhigh rstn pin clamped low high low x normal, standby, flash go to reset mode after t_rstn_filt config 1, 2, 3, 4 start ? up go to reset mode after t_rstn_filt; activate fso sw development start ? up go to reset mode after t_rstn_filt; do not activate fsox config 1 and 3 trying to exit reset mode keep reset mode; activate fsox after t_rstn_clampedlow config 2 and 4 trying to exit reset mode keep reset mode go to fail ? safe after t_rstn_clampedlow sw development trying to exit reset mode keep reset mode do not go to fail ? safe do not activate fsox www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 21 event flags and interrupt requests an interrupt request can be signaled by the NCV7471 to the attached microcontroller via the open ? drain output pin intn. the active level of the intn pin is logical low. pin intn is provided with an internal pull ? up resistor. an additional external pull ? up is recommended ? see figure 2. the interrupt request generation is available during the start ? up, normal, standby and flash modes. the following events are handled by the interrupt sub ? system: ? can, lin and wu wakeups (cannot be masked) ? timer wakeup in standby mode (cannot be masked) ? vout2 supply crossing the under ? voltage level in either direction if vout2 is on ? vout2 supply crossing the over ? voltage level in either direction ? txd dominant time ? out for can or linx (valid only if the respective transceiver is configured in its normal mode) ? the junction temperature crosses the thermal warning level in either direction ? internal dc/dc converter signals changing their status ? these events indicate entering or leaving limit conditions for both stages of the converter (run ? state of the boost, overload of the boost or buck, out ? of ? regulation state of buck) ? watchdog missed in sw development configuration if an event is encountered, it always causes the corresponding spi flag go high. if the event is masked by the spi interrupt mask setting (the corresponding mask bit is low), pin intn will not be forced low and no interrupt request will be issued. the interrupt flag remains available for later readout until the next read ? and ? clear access through the spi interface. txd dominant time ? out flags will remain set even after a read&clear access if the excessively long dominant signal is still present on the corresponding txd pin. note, that wakeup events cannot be masked. an overview of event flags is given in table 10. in case an un ? masked interrupt event takes place, not only the corresponding event flag is set high, but also intn pin is driven low for t_intn_active , indicating an interrupt request to the microcontroller. the microcontroller software is expected to read and clear the interrupt status register, otherwise the interrupt request remains pending (with the exception of flagres_swd). pending or new interrupt requests will lead to a new intn low pulse no sooner than t_intn_inactive after the previous pulse. in this way, it is ensured that multiple new or pending interrupts will not slow ? down the execution of the application software. control of the intn pin in conjunction with the internal flags is illustrated in figure 14. figure 14. interrupt request handling in start ? up, normal, standby and flash modes u1 u2 m1 read&clear u1, m1 read u2 read&clear u2 masked events unmasked events intn spi access u3 read&clear u3 u4 t_intn_active t_intn_active t_intn_active t_intn_inactive t_intn_inactive irq due to pending u2 request irq due to u3 and u4 events operating mode start ? up/normal/standby/flash in order to prevent that a pending interrupt request gets ignored by the application software, NCV7471 offers the following mechanisms: ? all event flags are preserved when transitioning from start ? up to normal mode ? see figure 15. ? all event flags are preserved when transitioning from standby to normal mode ? see figure 15. ? all event flags are preserved when transitioning from normal to standby mode. if standby mode is requested while an un ? masked interrupt is pending, a new interrupt request is issued according the t_intn_inactive timing ? see figure 16. ? if sleep mode is requested while a wakeup flag is pending, the chip immediately performs a ?wakeup from sleep? mode sequence ? see figure 17. in this way, the information on the pending wakeup is not missed by the application. any transition through the reset mode erases all spi event flags, except the wakeup flags, and sets all maskable events to masked (i.e. not causing an interrupt request). www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 22 table 10. event flags summary event flag bit related status bit (note 1) related interrupt mask bit set condition reset condition txdx time ? out flagto_txdc none intento_txdc txdx (note 2) pin is kept low for longer than the time ? out period and corresponding transceiver in normal mode read&clear access to register status0 and {txdx (note 2) dominant time ? out condition disappeared or transceiver mode other then ?normal?} flagto_txdl1 intento_txdl1 flagto_txdl2 intento_txdl2 smps flagbuck_noreg statbuck_noreg intenbuck_noreg buck smps stage enters or leaves range of no regulation (i.e. extreme switching duty cycle); indicates (in)ability to reach nominal vout read&clear access to register status0 flagbuck_ol statbuck_ol intenbuck_ol buck smps stage enters or leaves over ? load condition (i.e. current limitation encountered or disappeared) flagboost_run statboost_run intenboost_run boost smps stage changes activity ? it starts or stops flagboost_ol statboost_ol intenboost_ol boost smps stage enters or leaves over ? load condition (i.e. current limitation encountered or disappeared) flagtwar stattwar intentwar junction temperature crosses the warning level in either direction flagres_swd (note 4) none intenres_swd incorrect watchdog service encountered and device in sw development configuration vout2 flagvout2_uv statvout2_uv intenvout2_uv vout2 under ? voltage detector changes state in either direction and vout2 is switched on flagvout2_ov statvout2_ov intenvout2_ov vout2 over ? voltage detector changes state in either direction flagspifail (note 5) none intenspifail spi frame failure occurs: ? number of spi clocks different from 0 or 16, or ? sck high when csn changes state wakeups flagwakewu none none wu wakeup detected (note 3) read&clear access to register status1 flagwakecan can wakeup detected (note 3) flagwakelin1 lin1 wakeup detected (note 3) flagwakelin2 lin2 wakeup detected (note 3) flagwaketimer timer wakeup detected (note 3) 1. when a related status bit exists, the event is linked to a change (in either direction) of the status bit. even if the event flag is cleared, the corresponding status bit still indicates the current status of the observed feature and can be polled by spi at any time. 2. ?x? = ?c?, ?l1 or ?l2?. in case of lin transceivers, the time ? out feature can be enabled/disabled by spi. 3. the respective wakeup source must be enabled through the corresponding control spi register ? timer wakeup in control0; can, lin1/2 and wu wakeups in control1 4. for a missed wd in sw development, intn pulse is generated only once per event ? it is not repeated even if the corresponding flag is still set. new intn pulse occurs only if wd is missed again in sw development. 5. during vout power ? up (e.g. when going from shut ? down mode, or when waking ? up from sleep or fail ? safe mode), flagspifail can be set because of transient toggling of internal csn and sck signals. it is therefore recommended to ignore flagspifail immediatel y after vout power ? up, until the sta tus0 register is reset. except flagspifail, the remaining spi register content is not influenced by the possible internal toggling of csn and sck signals during power ? up. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 23 figure 15. interrupt request handling during a transition to normal mode irq due to pending u1 request u1 read&clear u1 intn spi access t_intn_inactive t_intn_active t_intn_active go to normal or flash start ? up/standby normal/flash unmasked events operating mode figure 16. transition to standby mode with a pending interrupt request u1 read&clear u1 intn spi access t_intn_inactive t_intn_active t_intn_active go to standby irq due to pending u1 request normal standby unmasked events operating mode figure 17. attempted transition to sleep mode with a pending wakeup flag u1 wakeup event intn spi access go to normal reset start ? up rstn rstn due to pending wakeup interrupt flags and masks reset in spi read&clear wakeup flag sleep (transient) sleep after reset, wu and can/lin wakeups disabled; pending flags will not cause additional intn pulse operating mode www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 24 junction temperature monitoring the device junction temperature is monitored in order to avoid permanent degradation or damage of the chip. two distinct junction temperature thresholds are used: ? thermal warning level tj_war . the status of the current junction temperature compared with the tj_war threshold is available in the corresponding spi status register. a change of the junction temperature across the warning threshold in either direction sets the spi bit flagtwar. if not masked, an interrupt request can be generated in order to signal to the application that the junction temperature exceeded or cooled below the warning level. ? thermal shut ? down level tj_sd . junction temperature exceeding the shut ? down level puts the chip into fail ? safe mode. in this specific case, no wakeups are detected in the fail ? safe mode; the mode is auto ? matically left only when the junction cools down below the warning level, thus providing a thermal margin for the application software to cope with the event. the junction temperature monitoring circuit is active in all operating modes with vout supply switched on (power ? up, reset, start ? up, standby, flash) and also in the fail ? safe, provided that it has been entered as the consequence of a thermal shut ? down. the function of the junction temperature monitoring of NCV7471 is shown in figure 18. figure 18. junction temperature monitoring power ? up, reset, start ? up, normal, stand ? by, flash tjunction below warning threshold spi twar status bit = 0 tjunction above warning threshold spi twar bit = 1 fail ? safe mode tjunction above shutdown threshold no wakeup detection vout, vout2: off rstn: low (if enabled) flagtwar ? > 1; interrupt request (if enabled) tj > tj_war tj < tj_war tj > tj_sd tj < tj_war flagtwar ? > 1; interrupt request www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 25 fso1/2/3 ? fail ? safe outputs NCV7471 of fers three digital outputs dedicated to control a fail ? safe circuitry in the application under specific failure conditions. all three outputs are high ? voltage low ? side open drain drivers simultaneously ac tivated by a common internal signal fso_internal and providing different behavior: ? fso1 is constantly pulled low if fso_internal is active ? fso2 provides 50% rectangular signal with 1.25 hz frequency ? fso3 provides 20% rectangular signal with 100 hz frequency figure 19 illustrates the fsox pins function with respect to the internal fso_internal signal. figure 19. operation of fsox pins fso_internal is set to high as soon as a failure condition is recognized or as soon as an spi command is given to activate fso. overview of situations leading to fso_internal activation is given in table 11. the handling of the different failure conditions depends on the chip configuration (see the configuration mode section) ? specifically in the sw development configuration, the watchdog ? related failures and ?rstn clamped low? failure do not lead either to the fso_internal activation or to the fail ? safe mode entry. fso_internal signal will be reset (and the fsox outputs are subsequently de ? activated) under the following conditions: ? if fso_internal was set by setting the fso_on spi bit, it will be reset by writing ?0? to fso_on spi bit ? if fso_internal was set because of a failure condition, a read ? and ? clear access to the flagfso spi status bits will reset it. in start ? up mode, fso_internal high level limits spi functionality ? no register can be written or read&cleared with the exception of control0 register. attempts to perform a write or read&clear access to other registers will be ignored ? including attempts to reset bit fso_on or the flagfso.x bits. this condition ensures that the application software performs at least one successful watchdog service after a failure occurs. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 26 table 11. conditions for activation of fso_internal signal (?x? means ?don?t care?) fso activation event detected in modes detected in configurations fail ? safe mode entered thermal shutdown (tj > tjsd) power ? up reset start ? up normal standby flash all yes fatal vout failure ( vout < vout_fail for longer than t_vout_powerup ) power ? up all yes rstn clamped high reset all yes external rstn without previous wd service start ? up config 1,2,3,4 no rstn clamped low when trying to leave reset config 1,3 no config 2,4 yes 1 st watchdog missed start ? up normal flash standby (if wd on) config 1 no config 2 yes 2 nd watchdog missed start ? up normal flash standby (if wd on) config 3 no config 4 yes spi control bit fso set start ? up normal standby flash all no swdm and cfg digital inputs swdm and cfg pins are high ? voltage compliant digital inputs enabling NCV7471 flexibility with respect to the fail ? safe behavior. their logical value (compared to a low ? voltage digital threshold) is sensed and latched exclusively in the configuration operating mode ? i.e. when the chip leaves the shut ? down mode. subsequently, the latched values are not changed by any signal on swdm or cfg pin or by any spi communication. latched active level on swdm pin (i.e. high input level in the configuration mode) causes the chip to enter the sw development configuration regardless the state of cfg pin. when the latched swdm value is inactive (i.e. low in the configuration mode), the latched cfg value then controls whether a failure condition (missed watchdog or rstn clamped low) results in the fail ? safe entry or only in a reset pulse generation. more details are given in the configuration mode and fso1/2/3 ? fail ? safe outputs sections. spi ? serial peripheral interface spi frame format the serial peripheral interface ensures control of NCV7471 operating modes, configuration of its functions and read ? out of internal status and system information. the serial communication is achieved via spi frames shown in figure 20. as long as the csn chip select is high, the sck and sdi inputs are not relevant and the sdo output is kept high ? impedant. the signals on the sdi and sck inputs are taken into account only when csn chip select input is set to low. data incoming on pin sdi are then sampled at the falling edge of sck clock signal; output data are shifted to pin sdo at the rising edge of sck clock signal. bits are transmitted msb (most significant bit) first. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 27 figure 20. spi frame format a2 a1 a0 read only di11 di10 di9 di8 di7 di6 di5 di4 di3 di2 di1 di0 do11 do10 do9 do8 do7 do6 do5 do4 do3 do2 do1 do0 hz hz header data x x csn sck sdi a2 a1 a0 read only spi ready sdo one frame consists of exactly sixteen bits transferred from the microcontroller to NCV7471 through input pin sdi. the input bits are interpreted as follows: ? immediately after csn falling edge, sdo pin shows an internal ?spi ready? flag. under normal conditions, when the inter ? frame space is respected, the ?spi ready? flag is set to high and the device is available for spi communication. if the spi inter ? frame space is violated, the previous spi data might not be processed at the moment of the next csn low level; this situation is signaled by low ?spi ready? flag. if the application software still attempts to perform spi communication, incoming data will be completely ignored and the sdo signals ?low? throughout the spi frame. the status of the flag is latched at the csn falling edge ? the application software might use short low pulses on csn (without sck) in order to poll the flag. ? four most significant bits form the header of the spi frame. during the reception of the header bits, the sdi signal is looped back to the sdo pin starting with the first rising edge of sck ? except for the internal delay, signals sdo and sdi are equal during the header transmission. the header bits have the following function: ? bits a2, a1, and a0 form a 3 ? bit address of an internal spi register. NCV7471 contains eight twelve ? bit registers addressable by these three header bits. ? bit ?readonly? contains the ?read ? only? flag. if readonly=high, the current spi frame represents a read ? only access to the spi register. if readonly=low, then the current spi frame represents either a write or read ? and ? clear access to an spi register ? the distinction between ?write? and ?read ? and ? clear? access depends on the specific register. ? bits di11 ? di0 are the spi data. in case of a read ? only or read ? and ? clear access, these bits are ignored. in case of a write ? frame, these bits are taken as the new spi register content at the moment of the csn rising edge (when the frame is considered finished). regardless the access type, the output data do11 ? do0 represent the spi register content as valid at the beginning of the spi frame. the output bits are shifted ? out at the rising edge of the sck clock so that they can be sampled by the microcontroller at the sck falling edge. the following checks are performed on every spi frame: ? the sck clock input must be low at both edges of the csn chip select signal ? there must be exactly sixteen sck clock cycles when csn=low (or no sck edge if only the ?spi ready? flag is polled). if any of the above conditions is not fulfilled, the spi frame is considered incorrect and the ?spi fail? event is internally generated. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 28 spi register mapping table 12. spi registers mapping address register name register content a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 control0 opmode.2 opmode.1 opmode.0 wd_mod.1 wd_mod.0 wd_per.2 wd_per.1 wd_per.0 checksum reserved reserved reserved input res_src.3 res_src.2 res_src.1 res_src.0 output 0 0 1 control1 reserved envout2 modwu.1 modwu.0 modcan.1 modcan.0 enlin_lslp disto_txdl modlin2.1 modlin2.0 modlin1.1 modlin1.0 0 1 0 control2 reserved reserved reserved reserved reserved fso_on fast_fso vout_res.1 vout_res.0 moddcdc.1 moddcdc.0 enboost 0 1 1 control3 intento_txdc intento_txdl1 intento_txdl2 intenbuck_noreg intenbuck_ol intenboost_run intenboost_ol intentwar intenres_swd ntenvout2_uv intenvout2_ov intenspifail 1 0 0 status0 flagto_txdc flagto_txdl1 flagto_txdl2 flagbuck_noreg flagbuck_ol flagboost_run flagboost_ol flagtwar flagres_swd flagvout2_uv flagvout2_ov flagspifail 1 0 1 status1 reserved reserved reserved flagfso.3 flagfso.2 flagfso.1 flagfso.0 flagwakewu flagwakecan flagwakelin1 flagwakelin2 flagwaketimer 1 1 0 status2 reserved statvs_low statbuck_noreg statbuck_ol statboost_run statboost_ol statswdm statcfg statwu stattwar statvout2_uv statvout2_ov 1 1 1 general purpose gpd.11 gpd.10 gpd.9 gpd.8 gpd.7 gpd.6 gpd.5 gpd.4 gpd.3 gpd.2 gpd.1 gpd.0 note: ?reserved? bits in input data are ignored; they are set to low in output data. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 29 table 13. spi registers initialization address register name initialization readonly bit a2 a1 a0 initialized in (note 6) initial content low (note 7) high 0 0 0 control0 reset mode (except flash mode entry) watchdog set to time ? out @ 256 ms nominal mode and watchdog settings (bits di11 ? di4) written into the register if checksum (bit di3) is ok. input bits di2 ? di0 ignored. input data ignored; current register content sent to spi output 0 0 1 control1 power ? up mode all bits low (note 9) bits di11 ? di0 written into the register reset mode all bits low (note 9) 0 1 0 control2 configuration all bits low bits di11 ? di0 written into the register sleep all bits low 0 1 1 control3 reset mode all bits low bits di11 ? di0 written into the register 1 0 0 status0 reset mode all bits low read&clear access; all bits reset to low (note 8); input data ignored 1 0 1 status1 configuration mode all bits low read&clear access; all bits reset to low; input data ignored 1 1 0 status2 n.a. reflects status of internal blocks input data ignored 1 1 1 general purpose configuration mode register filled with device id data bits di11 ? di0 written into the register 6. in modes not explicitly listed in ?initialized in? column, the register content is preserved 7. regardless the access type (the ?readonly? bit), the current register content is always sent to the spi output 8. bits containing txd dominant timeout flags will remain set if the excessively long dominant signal persists on the respective txdx pin 9. exception: in sw development configuration, control1 bits modcan.x, modlin1.x and modlin2.x are all set to ?high?, correspond ing to the default ?normal? mode of all transceivers www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 30 control0 register (address 000) by a write access to the control0 register (?readonly? = low), the application software can control the operating mode of NCV7471 and the watchdog settings. a write access represents a watchdog service. an operating mode change is therefore always synchronized with the watchdog trigger message. in order to provide more safety to the mode control, the input data are protected with a check ? sum (input bit di3). the checksum must correspond to the following formula (symbol ? ? denoting the exclusive ? or operation): in case of incorrect checksum in written data, the device reacts identically to a wrong opmode situation. during a read ? only access to the control0 register (?readonly? = high), the input data are completely ignored and no check is performed on them. the output data of the control0 register ? regardless the access type ? indicate the current operating mode, the current watchdog settings and the cause of the last reset. the initialization of the control0 register content is performed after every reset, when the watchdog type is fixed to time ? out, and the watchdog period to nominally 256 ms. di3 = di11 di10 di9 di8 di7 di6 di5 di4 table 14. control0 register: opmode.x encoding opmode.2 opmode.1 opmode.0 opmode.x in input data opmode.x in output data requested mode reaction in start ? up reaction in normal reaction in standby reaction in flash current mode 0 0 0 forbidden ?wrong opmode? reset start ? up 0 0 1 normal go to normal keep normal go to normal return from flash via reset and start ? up normal 0 1 0 standby ?wrong opmode? reset go to standby keep standby ?wrong opmode? reset standby 0 1 1 sleep ?wrong opmode? reset go to sleep ?wrong opmode? reset not used 1 0 0 flash go to flash via reset go to flash via reset ?wrong opmode? reset keep flash flash 1 0 1 fail ? safe in sw development configuration, go to fail ? safe; otherwise ?wrong opmode? reset not used 1 1 0 reset go to reset not used 1 1 1 configuration go to configuration go to configuration ?wrong opmode? reset not used table 15. control0 register: wd_mod.x encoding wd_mod.1 wd_mod.0 watchdog timer mode limitations (if not respected, the write access is considered as a missed watchdog) 0 0 watchdog off can be used only with a standby or a sleep mode request 0 1 window watchdog can be used only for normal mode request 1 0 time ? out watchdog must be used with every flash mode request; can be used with a standby or normal mode request; default in start ? up mode 1 1 timer wakeup can be used only with a standby mode request www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 31 table 16. control0 register: wd_per.x encoding wd_per.2 wd_per.1 wd_per.0 watchdog peri- od nominal duration note 0 0 0 wd_per_0 8 ms 0 0 1 wd_per_1 16 ms 0 1 0 wd_per_2 32 ms 0 1 1 wd_per_3 64 ms 1 0 0 wd_per_4 128 ms 1 0 1 wd_per_5 256 ms wd_per_5 is automatically used in start ? up mode 1 1 0 wd_per_6 512 ms can be used only for standby and flash modes (otherwise the watchdog spi frame is considered wrong) 1 1 1 wd_per_7 1024 ms table 17. control0 register: res_src.x encoding res_src.3 res_src.2 res_src.1 res_src.0 cause of the last rstn pulse reset event priority (note 10) 0 0 0 0 v_mid under ? voltage recovery (v_in connection) 12 0 0 0 1 external reset outside start ? up mode (not accompanied by fso activation) 10 0 0 1 0 recovery from fail ? safe (through wakeup or thermal shutdown recovery) 8 0 0 1 1 wakeup from sleep 7 0 1 0 0 flash mode requested 6 0 1 0 1 flash mode exited 5 0 1 1 0 reset mode requested 4 0 1 1 1 configuration requested 3 1 0 0 0 failed watchdog (wd missed, wrong wd mode or period requested) ? will not be used in sw development configuration (note 11) 2 1 0 0 1 wrong operating mode requested; wrong checksum during write access to the mode con- trol register 1 1 0 1 0 external reset in start ? up mode (accompanied by fso activation if not in sw develop- ment configuration) 9 1 0 1 1 reserved ? 1 1 0 0 reserved ? 1 1 0 1 reserved ? 1 1 1 0 reserved ? 1 1 1 1 vout under ? voltage recovery 11 10. the ?reset event priority? reflects the order, in which the reset events are processed by the on ? chip digital. in case more events occur simultaneously, the one with the lower priority number would be stored in control0 register. 11. wd period and wd mode settings are not checked in the following situations: configuration mode request, reset mode request, flash exit (i.e. normal mode request in the course of flash mode) www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 32 control1 register (address 001) control1 register defines the mode of individual can and linx transceivers, of the vout2 regulator and the wu pin. the encoding of the control1 bits is defined in table 18. table 18. control1 register encoding envout2 vout2 control 0 vout2 regulator is off 1 vout2 regulator is on modwu.1 modwu.0 wu mode control 0 0 wu wakeup detection disabled 0 1 wu monitored for falling edge 1 0 wu monitored for rising edge 1 1 wu monitored for both edges modcan.1 modcan.0 can transceiver mode 0 0 can transceiver in off mode 0 1 can transceiver in wakeup mode 1 0 can transceiver in receive ? only mode 1 1 can transceiver in normal mode enlin_lslp lin slope control ? common for both lin channels 0 lin transmission with normal bus signal slopes (according lin2.1 specification) 1 lin transmission with slow bus signal slopes (for limited bit ? rate) disto_txdl lin dominant time ? out control ? common for both lin channels 0 dominant time ? out applied on txdl pins 1 dominant time ? out not ? applied on txdl pins ? unlimited dominant symbols can be transmitted modlinx.1 modlinx.0 linx transceiver mode (x=1,2) 0 0 linx transceiver in off mode 0 1 linx transceiver in wakeup mode 1 0 linx transceiver in receive ? only mode 1 1 linx transceiver in normal mode control1 register is initialized at every reset event with all ? zeros content www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 33 control2 register (address 010) content of control2 register is defined in table 19. the control2 register content is initialized to all ? zeros content in the configuration and sleep modes. table 19. control2 register encoding bit definition fso_on if high, fsox outputs are forced active fast_fso if high, already the 1 st missed watchdog will be treated as a failure; the exact reaction depends on the configuration vout_res.1 vout_res.0 selection of vout under ? voltage threshold for rstn pin 0 0 vout_res4 threshold selected (the lowest threshold) for rstn indication 0 1 vout_res3 threshold selected for rstn indication 1 0 vout_res2 threshold selected for rstn indication 1 1 vout_res1 threshold selected for rstn indication moddcdc.1 moddcdc.0 dcdc converter mode selection 0 0 dcdc converter switching with fixed frequency 0 1 converter switching frequency modulated with modulation depth dmod_dcdc_1 1 0 converter switching frequency modulated with modulation depth dmod_dcdc_2 1 1 converter switching frequency modulated with modulation depth dmod_dcdc_3 enboost if high, boost (step ? up) stage of the dcdc converter is enabled control3 register (address 011) the individual bits in the control3 register determine whether the corresponding interrupt event leads to an interrupt request via intn pin or if it is only stored as a flag for later spi retrieval. if the bit is high, the interrupt request is enabled. all bits of the control3 register are reset to low at every reset event (i.e. all interrupt sources are disabled). table 20. control3 register encoding bit definition intento_txdc enables interrupt after dominant time ? out on txdc intento_txdl1 enables interrupt after dominant time ? out on txdl1 intento_txdl2 enables interrupt after dominant time ? out on txdl2 intenbuck_noreg enables interrupt after a change of the internal converter signal indicating, that the buck stage cannot reach the output nominal voltage (typically due to too low line voltage) intenbuck_ol enables interrupt after a change of the internal converter signal indicating, that the buck stage is overloaded intenboost_run enables interrupt when the boost stage is activated or de ? activated ? indicating a c hange in supply line conditions intenboost_ol enables interrupt after a change of the internal converter signal indicating, that the boost stage is overloaded intentwar enables interrupt when the junction temperature crosses the thermal warning level (in either direction) intenres_swd in sw development configuration only ? incorrect watchdog service will lead to an interrupt request (outside sw development configuration, this event would lead to reset). intenvout2_uv enables interrupt when vout2 crosses its under ? voltage level (in either direction). event registered only if vout2 is on. intenvout2_ov enables interrupt when vout2 crosses its over ? voltage level (in either direction). intenspifail enables interrupt when an spi frame failure is encountered www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 34 status0 register (address 100) status0 bits latch information on individual events which can potentially lead to interrupt requests. all bits have their position corresponding to the control3 register bits. the details of the status0 bits are given in t able 21. a read ? and ? clear access to status0 register is considered ?interrupt service? for all pending interrupt requests. a read ? only access does not change the flags and the active interrupt requests remain pending. specifically, flags corresponding to dominant time ? outs can be cleared only when the respective time ? out disappeared; otherwise, they will remain set even after read&clear access and, if enabled, the interrupt linked to them will remain pending. status0 register is reset to all ? zeros content at every reset event. table 21. status0 register encoding bit definition flagto_txdc txdc dominant time ? out occurred. the bit can be cleared only when the time ? out condition disappeared (or when the can transceiver mode was changed to other than ?can normal?). flagto_txdl1 txdl1 dominant time ? out occurred. the bit can be cleared only when the time ? out condition disappeared (or when the lin1 transceiver mode was changed to other than ?lin normal?). flagto_txdl2 txdl2 dominant time ? out occurred. the bit can be cleared only when the time ? out condition disappeared (or when the lin2 transceiver mode was changed to other than ?lin normal?). flagbuck_noreg flags a change of the internal converter signal indicating, that the buck stage cannot reach the output nominal voltage (typically due to too low line voltage) flagbuck_ol flags a change of the internal converter signal indicating, that the buck stage is overloaded flagboost_run boost stage toggled its state (was activated or de ? activated) ? indicating a change in supply line conditions flagboost_ol flags a change of the internal converter signal indicating, that the boost stage is overloaded flagtwar junction temperature crossed the thermal warning level (in either direction) flagres_swd in sw development configuration only ? incorrect watchdog service occurred flagvout2_uv vout2 crossed its under ? voltage level (in either direction). event registered only if vout2 is on. flagvout2_ov vout2 crossed its over ? voltage level (in either direction). flagspifail spi frame failure was encountered (note 12) 12. during vout power ? up (e.g. when going from shut ? down mode, or when waking ? up from sleep or fail ? safe mode), flagspifail can be set because of transient toggling of internal csn and sck signals. it is therefore recommended to ignore flagspifail immediatel y after vout power ? up, until the sta tus0 register is reset. except flagspifail, the remaining spi register content is not influenced by the possible internal toggling of csn and sck signals during power ? up. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 35 status1 register (address 101) status1 register contains flags for fail ? safe events and wakeups. a specific bit (flag) is set high when the corresponding event was recognized and is set to low only when the status1 register is read and cleared. the status1 register is initialized in configuration mode to all ? zeros content. it is not reset in reset or start ? up mode in order to preserve the wakeup and failure flags coming from sleep or fail ? safe mode. encoding of the fso ? related flag bits is defined in table 22. table 22. status1 register: flagfso.x encoding flagfso.3 flagfso.2 flagfso.1 flagfso.0 failure event leading to fsox activation 0 0 0 0 no failure, fsox inactive (unless over ? ruled by fso_on bit) 0 0 0 1 fsox active due to missed watchdog; without entry into fail ? safe mode 0 0 1 0 fsox active due to ?rstn clamped low?; without entry into fail ? safe mode 0 0 1 1 fsox active due to external reset in start ? up mode; without entry into fail ? safe mode (not detected in sw development configuration) 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 fsox active; coming from fail ? safe mode requested by spi 1 0 0 1 fsox active; coming from fail ? safe mode caused by missed watchdog 1 0 1 0 fsox active; coming from fail ? safe mode caused by ?rstn clamped low? 1 0 1 1 fsox active; coming from fail ? safe mode caused by ?rstn clamped high? 1 1 0 0 fsox active; coming from fail ? safe mode caused by thermal shutdown 1 1 0 1 fsox active; coming from fail ? safe mode caused by vout undervoltage time ? out (short ? circuit detected) 1 1 1 0 reserved 1 1 1 1 reserved wakeup flag bits are summarized in table 23. detection of individual wakeup events is controlled by transceiver mode settings (for lin and can wakeup), wu pin mode settings (for wu wakeup) and watchdog settings (for timer wakeup). a wakeup event is indicated either by an interrupt request (in normal or standby mode) or by a reset pulse (wakeups from sleep mode). in normal and standby mode, a wakeup causes pending interrupt request until a read ? and ? clear access to status1 register. table 23. status1 register: wakeup flags bit definition flagwakewu wakeup on wu pin was detected (for non ? zero setting of modwu.x spi bits) flagwakecan wakeup on can bus was detected (can transceiver in ?can wakeup? mode) flagwakelin1 wakeup on lin1 bus was detected (lin1 transceiver in ?lin wakeup? mode) flagwakelin2 wakeup on lin2 bus was detected (lin2 transceiver in ?lin wakeup? mode) flagwaketimer wakeup by timer (?timer wakeup? selected through control0 register) www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 36 status2 register (address 110) status2 register bits reflect the state of several internal blocks of the device. read ? and ? clear or write access does not change the register content. the status2 bits are defined in table 24. table 24. status2 register encoding bit definition statvs_low indication of the vs monitoring output. if vs< vs_mon , then statvs_low = 1 statbuck_noreg indication of the buck dcdc stage not being able to reach the nominal vout voltage statbuck_ol indication of the buck dcdc stage overload statboost_run indication that the boost dcdc stage is running (boost stage must be enabled and the input voltage requires step ? up operation) statboost_ol indication of the boost dcdc stage overload statswdm logical level of the swdm pin latched during configuration mode statcfg logical level on the cfg pin latched during configuration mode (in config 1,2,3,4) or current logical level on cfg pin (in sw development) statwu logical level on the wu pin stattwar output of the thermal warning comparator (if high, junction temperature is above the warning level) statvout2_uv output of the vout2 under ? voltage comparator (if high, vout2 is below the under ? voltage level). available only if vout2 regulator is on. statvout2_ov output of the vout2 over ? voltage comparator (if high, vout2 is above the over ? voltage level) general purpose register (address 111) general purpose register allows storing general 12 ? bit information in the NCV7471 memory. the register is initialized only in configuration mode, when a device version id is loaded. any data written to the register overwrite the initial content and are kept throughout the operation of the device until device enters shut ? down mode or until configuration is requested. the device id of the final silicon version is 0x103 in hexadecimal format. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 37 table 25. absolute maximum ratings symbol parameter min max units vmax_vs maximum voltage at vs pin ? 0.3 40 v vmax_vs_vout2 maximum voltage at vs_vout2 pin ? 0.3 40 v vmax_boost maximum voltage at boost pin ? 0.3 v_mid+2 v vmax_v_mid maximum voltage at v_mid pin ? 0.3 40 v vmax_buck maximum dc voltage at buck pin maximum transient voltage on buck pin (note 13) ? 1 ? 3 v_mid+0.3 v vmax_vout maximum voltage at vout pin ? 0.3 6 v vmax_vout2 maximum voltage at vout2 pin ? 1 40 v vmax_vcc_can maximum voltage at vcc_can pin ? 0.3 6 v vmax_canh, vmax_canl maximum voltage at can bus pins (0 < vcc_can < 5.25 v; no time limit) ? 50 50 v vmax_linx maximum voltage at lin bus pins ? 45 45 v vmax_fsox maximum voltage at fsox pins ? 0.3 40 v vmax_wu maximum voltage at wu pin ? 40 40 v vmax_cfg; vmax_swdm maximum voltage at cfg and swdm pins ? 0.3 40 v vmax_digin maximum voltage at digital input and open ? drain pins (txdlx, txdc, sck, sdi, intn, rstn, uvn_vout) ? 0.3 6 v vmax_digout maximum voltage at digital push ? pull output pins (rxdlx, rxdc, sdo) ? 0.3 vout+0.3 v vmax_csn maximum voltage at csn pin ? 0.3 40 v tjunc_max junction temperature ? 40 +170 c v_esd system esd on pins canh, canl, lin1, lin2, vout2, vs, vs_vout2, wu as per iec 61000 ? 4 ? 2: 330 / 150 pf 6 kv human body model on pins canh, canl, lin1, lin2 stressed towards gnd with 1500 / 100 pf 6 kv human body model on pins vs, vs_vout2, wu stressed towards gnd with 1500 / 100 pf 4 kv human body model on all pins as per jesd22 ? a114 / aec ? q100 ? 002 2 kv charge device model on all pins as per jesd22 ? c101 / aec ? q100 ? 011 500 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 13. buck pin tolerates transient voltage excursions below ? 1 v, caused by the buck ? converter switching and the non ? ideal characteristics of diode d2 (see figure 2). it is not implied that a hard voltage source of less than ? 1 v can be connected to the pin externally. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 38 table 26. operating ranges symbol parameter min max units vop_v_in_boostbuck v_in operating voltage for boost/buck operation 2.5 28 v vop_v_in_buck v_in operating voltage for buck ? only operation 6 28 v vop_vs_vout2 operating dc voltage at vs_vout2 pin 6 28 v vop_boost operating voltage at boost pin 0 v_mid+v_d1 v vop_v_mid operating voltage at v_mid pin 5.5 28 v vop_buck operating voltage at buck pin ? v_d2 v_mid v vop_vout regulated voltage at vout2 supply output 4.9 5.1 v vop_vout2 regulated voltage at vout2 supply output 4.9 5.1 v vop_vcc_can_normal operating voltage at vcc_can pin for normal and receive only can modes 4.75 5.25 v vop_vcc_can_lowpower operating voltage at vcc_can pin for wakeup and off can modes 0 5.25 v vop_canh, vop_canl operating voltage at can bus pins 0 vcc_can v vop_linx operating voltage at lin bus pins 0 vs v vop_fsox operating voltage at fsox pins 0 vs v vop_wu operating voltage at wu pin 0 vs v vop_cfg; vop_swdm operating voltage at cfg and swdm pins 0 vs v vop_digio operating voltage at digital input and output pins (txdlx, rxdlx, txdc, rxdc, sck, csn, sdi, sdo, intn, rstn, uvn_vout) 0 vout v tjunc_op junction temperature ? 40 +150 c www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 39 electrical characteristics the characteristics defined in this section are guaranteed within the operating ranges listed in table 26, unless stated otherwise. positive currents flow into the respective pin. power supply table 27. supply monitoring electrical characteristics symbol parameter conditions min typ max unit v_mid_porh v_mid threshold for the power ? up of the circuit v_mid rising 3.3 3.7 4 v v_mid_porl v_mid threshold for the shut ? down of the circuit v_mid falling 2.2 2.65 3 v vs_mon monitoring level on vs pin defining the operation of the lin transceivers vs falling 3 5.2 v vs_mon_hys hysteresis of the vs monitor 0.12 v t_vs_mon_filt vs monitoring filter time 16 25 s vout_res1 vout monitoring threshold 1 vout falling 4.55 4.65 4.75 v vout_res2 vout monitoring threshold 2 vout falling 3.8 3.9 4.0 v vout_res3 vout monitoring threshold 3 vout falling 3.35 3.45 3.55 v vout_res4 vout monitoring threshold 4 vout falling 3.0 3.1 3.2 v vout_res_hys vout monitoring threshold hysteresis 0.03 0.1 0.14 v vout_fail vout failure threshold vout rising 2 v t_vout_uv_filt undervoltage detection filter time 16 25 s t_vout_powerup vout undervoltage time ? out for short ? circuit re- cognition w.r.t. vout_fail threshold 1.35 1.5 1.65 s t_vout_reset rstn pulse extension 4.5 5 5.5 ms vout2_uv vout2 under ? voltage threshold vout2 falling 4.45 4.65 4.75 v vout2_uv_hys vout2 under ? voltage threshold hysteresis 0.1 v t_vout2_uv_filt undervoltage detection filter time 16 25 s vout2_ov vout2 over ? voltage threshold 7 v vout2_ov_hys vout2 over ? voltage threshold hysteresis 0.1 v t_vout2_ov_filt overvoltage detection filter time 32 50 s www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 40 table 28. dc/dc converter electrical characteristics symbol parameter conditions min typ max unit vout dcdc output voltage NCV7471 in normal or standby; suitable external components for the required load current and input voltage used. 4.9 5.0 5.1 v i_out dcdc output current available for ex- ternal loads (see figure 2) NCV7471 in normal or standby; function of external components 500 ma imaxpeak_boost maximum peak ? current detection threshold in boost stage tj 0 c tj > 0 c 1.6 1.6 2.2 2.0 a imaxpeak_buck maximum peak ? current detection threshold in buck stage 0.8 1.0 a v_mid_reg middle voltage level boosting active 6.175 6.5 6.825 v ron_boost on ? resistance of the boost ? stage switch 0.45 ron_buck on ? resistance of the buck ? stage switch 0.6 v_mid_ron v_mid level for parametrical on ? resist- ance of the converter switches 5 v fsw_dcdc constant switching frequency 450 485 520 khz fmod_dcdc modulation frequency modulation enabled via spi 8 10 13 khz dmod_dcdc_1 modulation depth 1 10 % dmod_dcdc_2 modulation depth 2 20 % dmod_dcdc_3 modulation depth 3 30 % table 29. vout2 regulator electrical characteristics symbol parameter conditions min typ max unit vout2 vout2 regulator output voltage vout2 regulator active; iload(vout2) 5 ma 4.95 5.0 5.05 v vout2 regulator active; iload(vout2) 50 ma 4.9 5.0 5.1 v vout2_drop drop ? out voltage between vs_vout2 and vout2 iload(vout2) = 50 ma 0.35 0.6 v ilim_vout2 vout2 current limitation vout2 regulator active ? 80 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 41 table 30. current consumptions symbol parameter conditions min typ max unit i_vs (note 14) vs consumption in lin nor- mal mode lin1 and lin2 in normal mode; recessive on both lin buses 3.2 ma vs consumption with lin in wakeup or off mode lin1 and lin2 in lin ? wakeup or off mode; no activity on both lin buses 8 a i_vs_vout2 (note 14) vs_vout2 consumption if vout2 is on vout2 regulator is active 30 a + 1.1 x i(vout2) ? vs_vout2 consumption if vout2 is off vout2 regulator is off; vs_vout2 13.5 v; tj 85 c 1 a i_vcc_can (note 14) vcc_can consumption for dominant transmission can in normal mode driving dominant on the can bus; 60 load on the can pins 75 ma vcc_can consumption for recessive transmission can in receive ? only mode or can in normal mode with recessive on the bus 10 ma vcc_can consumption in can wakeup mode can wakeup mode (can supplied from v_mid); device in standby or sleep mode; no wakeup detected 2 a i_in (notes 14, 16) dcdc input current in standby or normal mode NCV7471 in standby or normal mode; v_in (note 15) = 13.5 v; tj 85 c; no external vout load enboost = low; can in off mode 70 95 a dcdc input current in sleep mode NCV7471 in sleep mode; 5.5 v v_in (note 15) 18 v; tj 85 c; enboost = low; can in off mode 55 70 a i_in adder for can wakeup NCV7471 in normal, standby or sleep mode; 5.5 v v_in (note 15) 18 v; tj 85 c; can in wakeup mode 10 a i_in adder for boost stage NCV7471 in standby or normal mode; 5.5 v v_in (note 15) 18 v; tj 85 c; enboost = high; boost ? stage not switching 10 a 14. the supply currents are depicted in figure 2. 15. v_in is the dcdc input voltage ? see figure 2. 16. i_in is the total dcdc input current, covering the quiescent consumption of the device (through pins boost, v_mid, buck and vout), the current into the external load, and the losses associated with the dcdc conversion. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 42 can transceiver table 31. can transceiver electrical characteristics symbol parameter conditions min typ max unit can transmitter dc characteristics vo(reces)(canh) recessive bus voltage at pin canh v(txdc) = vout no load transmitter on 2 2.5 3 v vo(reces)(canh) recessive bus voltage at pin canh no load transmitter off ? 0.1 0 0.1 v vo(reces)(canl) recessive bus voltage at pin canl v(txdc) = vout no load transmitter on 2 2.5 3 v vo(reces)(canl) recessive bus voltage at pin canl no load transmitter off ? 0.1 0 0.1 v io(reces)(canh) recessive output current at pin canh ? 35 v < v(canh) < 35 v (note 17), 0 v < vcc_can < 5.25 v ? 2.5 ? 2.5 ma io(reces)(canl) recessive output current at pin canl ? 35 v < v(canl) < 35 v (note 17), 0 v < vcc_can < 5.25 v ? 2.5 ? 2.5 ma vo(dom)(canh) dominant output voltage at pin canh v(txdc) = 0 v 42.5 < r l < 60 3 3.6 4.25 v vo(dom)(canl) dominant output voltage at pin canl v(txdc) = 0 v 42.5 < r l < 60 0.5 1.4 1.75 v vo(dif)(bus_dom) differential bus output voltage (vcanh ? vcanl) v(txdc) = 0 v 42.5 < r l < 60 1.5 2.25 3 v vo(dif)(bus_rec) differential bus output voltage (vcanh ? vcanl) v(txdc) = vout recessive, no load ? 120 0 50 mv io(sc)(canh) short ? circuit output current at pin canh v(canh) = 0 v, v(txdc) = 0 v ? 120 ? 70 ? 45 ma io(sc)(canl) short ? circuit output current at pin canl v(canl) = 0 v, v(txdc) = 0 v 45 70 120 ma can receiver dc characteristics vi(dif)(th) differential receiver threshold voltage ? 5 v < v(canh) < 12 v ? 5 v < v(canl) < 12 v 0.5 0.7 0.9 v vihcm(dif)(th) differential receiver threshold voltage for high common mode ? 35 v < v(canh) < 35 v ? 35 v < v(canl) < 35 v (note 17) 0.4 0.7 1 v ri(cm)canh common mode input resistance at pin canh 15 26 37 k ri(cm)canl common mode input resistance at pin canl 15 26 37 k ri(cm)(m) matching between pin canh and pin canl common mode input resistance v(canh) = v(canl) ? 3 0 3 % ri(dif) differential input resistance 25 50 75 k ci(canh) input capacitance at pin canh vtxdc = vcc_can not tested ? 7.5 20 pf ci(canl) input capacitance at pin canl vtxdc = vcc_can not tested ? 7.5 20 pf ci(dif) differential input capacitance vtxdc = vcc_can not tested ? 3.75 10 pf ili input leakage current at pin canh and canl vcc_can = 0 v v(canh) = 5 v v(canl) = 5 v ? 5 0 5 a vi(dif)(th) differential receiver threshold voltage for the wakeup detection ? 12 v < v(canh) < 12 v ? 12 v < v(canl) < 12 v 0.4 0.8 1.15 v 17. in production, the parameter is measured for common ? mode range from ? 30 v to +35 v. the common mode range down to ? 35 v is guar- anteed by design. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 43 table 31. can transceiver electrical characteristics symbol unit max typ min conditions parameter can transceiver dynamic characteristics td(txdc ? buson) delay txdc to bus active c l = 100 pf between canh ? canl 5 85 110 ns td(txdc ? busoff) delay txdc to bus inactive c l = 100 pf between canh ? canl 5 30 110 ns td(buson ? rxdc) delay bus active to rxdc c(rxdc) = 15 pf 5 55 110 ns td(busoff ? rxdc) delay bus inactive to rxdc c(rxdc) = 15 pf 5 100 110 ns tdpd(txdc ? rxdc)dr propagation delay txdc to rxdc c l = 100 pf between canh ? canl 45 245 ns tdpd(txdc ? rxdc)rd propagation delay txdc to rxdc c l = 100 pf between canh ? canl 45 230 ns t_can_wake_dom dominant time for can wakeup lp mode vdif(dom) > 1.4 v 0.5 2.5 5 s lp mode vdif(dom) > 1.2 v 0.5 3 5.8 s t_can_wake_rec recessive time for can wakeup 0.5 2.5 5 s t_can_wake_timeout maximum length of the can wakeup pattern 0.9 1 1.1 ms t_txdc_timeout txdc dominant time for time out vtxdc = 0 v 2.9 3.7 4.5 ms 17. in production, the parameter is measured for common ? mode range from ? 30 v to +35 v. the common mode range down to ? 35 v is guar- anteed by design. figure 21. definition of can dynamic parameters vdiff= v(canh) ? v(canl) dominant 0.9 v 0.5 v recessive 50% recessive 50% txdc canh canl rxdc td(txdc ? buson) td(buson ? rxdc) td(txdc ? rxdc)rd td(txdc ? busoff) td(busoff ? rxdc) td(txdc ? rxdc)dr www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 44 lin transceivers table 32. linx transceiver electrical characteristics symbol parameter conditions min typ max unit linx transmitter dc characteristics vlin_dom_losup lin dominant output voltage txdlx = low; vs = 7.3 v 1.2 v vlin_dom_hisup lin dominant output voltage txdlx = low; vs = 18 v 2.0 v vlin_rec lin recessive output voltage txdlx = high; i(lin) = 0 ma vs ? 1.2 vs ? 0.3 v ilin_lim short circuit current limitation vs = 28 v 40 200 ma rslave internal pullup resistance lin normal or receive ? only mode 20 33 47 k ilin_off_dom lin output current, bus in dominant state normal lin mode, driver off; vs = 12 v ? 1 ma ilin_off_dom_slp lin output current, bus in dominant state lin wake mode, vs = 12 v ? 20 ? 15 ? 2 a ilin_off_rec lin output current, bus in recessive state driver off; vs < 18 v; vs < vlin < 18 v 1 a ilin_no_gnd lin current with missing gnd vs = gnd = 12 v; 0 v < vlin < 18 v ? 1 1 ma ilin_no_vbb lin current with missing vs vs = gnd = 0 v; 0 v < vlin < 18 v 5 a linx receiver dc characteristics vbus_dom bus voltage for dominant state 0.4 vs vbus_rec bus voltage for recessive state 0.6 vs vrec_dom receiver threshold lin bus going from recessive to dominant 0.4 0.6 vs vrec_rec receiver threshold lin bus going from dominant to recessive 0.4 0.6 vs vrec_cnt receiver center voltage (vrec_dom + vrec_rec)/2 0.475 0.525 vs vrec_hys receiver hysteresis vrec_rec ? vrec_dom 0.05 0.175 vs linx transceiver dynamic characteristics d1 duty cycle 1 = tbus_rec(max) / (2 x tbit) threc(min) = 0.744 x vs thdom(min) = 0.581 x vs tbit = 50 s v(vs) = 7 v to 18 v 0.396 0.5 d2 duty cycle 2 = tbus_rec(min) / (2 x tbit) threc(max) = 0.422 x vs thdom(max) = 0.284 x vs tbit = 50 s v(vs) = 7.6 v to 18 v 0.5 0.581 d3 duty cycle 3 = tbus_rec(max) / (2 x tbit) threc(min) = 0.778 x vs thdom(min) = 0.616 x vs tbit = 96 s v(vs) = 7 v to 18 v 0.417 0.5 d4 duty cycle 4 = tbus_rec(min) / (2 x tbit) threc(max) = 0.389 x vs thdom(max) = 0.251 x vs tbit = 96 s v(vs) = 7.6 v to 18 v 0.5 0.590 t_fall lin falling edge normal mode; vs = 12 v 22.5 s t_rise lin rising edge normal mode; vs = 12 v 22.5 s t_sym lin slope symmetry normal mode; vs = 12 v ? 4 0 4 s trec_prop_down propagation delay of receiver falling edge 0.1 6 s trec_prop_up rising edge 0.1 6 s trec_sym propagation delay symmetry trec_prop_down ? trec_prop_up ? 2 2 s t_lin_wake dominant duration for wakeup lin in wakeup mode 30 90 150 s t_txdlx_timeout txdlx dominant time ? out txdlx = low; lin dominant time ? out enabled 6 13 20 ms c_linx capacitance of the linx pins guaranteed by design; not tested in production 15 25 pf www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 45 figure 22. definition of linx duty cycle parameters linx t 50% thresholds of receiving node 1 thresholds of receiving node 2 txdlx t t bit t bit t bus_dom(max) t bus_rec(min) t bus_dom(min) t bus_rec(max) th rec(max) th dom(max) th rec(min) th dom(min) figure 23. definition of linx edge parameters t_fall t_rise linx t 60% 40% 60% 40% 100% 0% figure 24. definition of linx receiver timing parameters 50% trec_prop_up rxdlx t linx t vs trec_prop_down 60% vs 40% vs www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 46 digital control timing and spi timing table 33. digital control characteristics symbol parameter conditions min typ max unit t_wd_to t_wd_win duration of the total watchdog period wd_per_0 selected in spi 7.2 8 8.8 ms wd_per_1 selected in spi 14.4 16 17.6 ms wd_per_2 selected in spi 28.8 32 35.2 ms wd_per_3 selected in spi 57.6 64 70.4 ms wd_per_4 selected in spi 115.2 128 140.8 ms wd_per_5 selected in spi 230.4 256 281.6 ms wd_per_6 selected in spi 460.8 512 563.2 ms wd_per_7 selected in spi 921.6 1024 1126.4 ms f_fso2 fso2 toggling frequency fso_internal = 1 1.125 1.25 1.375 hz dc_fso2 fso2 duty cycle 45 50 55 % f_fso3 fso3 toggling frequency 90 100 110 hz dc_fso3 fso3 duty cycle 18 20 22 % t_intn_active active (low) pulse on intn pin 0.9 1 1.1 ms t_intn_inactive minimum time between two consecutive interrupt requests 4.5 5 5.5 ms t_rstn_filt rstn input signal filter time 1 10 s t_rstn_clamped_high timeout for ?rstn clamped high? detection 0.9 1 1.1 ms t_rstn_clamped_low timeout for ?rstn clamped low? detection 225 250 275 ms table 34. spi interface timing characteristics symbol parameter conditions min typ max unit tcsn_sck first spi clock edge after csn active 100 ns tsck_csn last spi clock edge to csn inactive 100 ns tcsn_sdo sdo output stable after csn active 100 ns tcsn_high inter ? frame space (csn inactive) 10 s tsck_high duration of spi clock high level 100 ns tsck_low duration of spi clock low level 100 ns tsck_per spi clock period 250 ns tsdi_set setup time of sdi input towards spi clock 50 ns tsdi_hold hold time of sdi input towards spi clock 50 ns tsck_sdo delay of sdo output stable after an spi clock edge 50 ns www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 47 figure 25. definition of spi timing parameters csn sck sdi sdo t sck_sdo t csn_sdo t csn_sck t sck_per t sck_csn t csn_high t sck_high t sck_low t sdi_hold t sdi_set thermal protection table 35. thermal protection characteristics symbol parameter conditions min typ max unit tj_war junction temperature for thermal warning 130 140 150 c tj_sd junction temperature for thermal shut ? down 150 160 170 c digital io pins table 36. electrical characteristics of low voltage digital inputs/outputs symbol parameter conditions min typ max unit vinl_pinx low ? level input threshold pinx = sdi, sck, csn, txdc, txdl1/2, rstn 0 0.8 v vinh_pinx high ? level input threshold 2 vout v rpullup_pinx integrated pull ? up resistor to vout pinx = csn, txdc, txdl1/2, intn, rstn, uvn_vout 55 100 185 k rpulldown_pinx integrated pull ? up resistor to vout pinx = sdi, sck 55 100 185 k ioutl_pinx low ? level output driving current pinx is logical low; forced vpinx = 0.4 v; pinx = sdo, rxdc, rxdl1/2, rstn, intn, uvn_vout 2 6 12 ma iouth_pinx high ? level output driving current pinx is logical high; forced vpinx = vout ? 0.4 v; pinx = sdo, rxdc, rxdl1/2 ? 12 ? 6 ? 2 ma ileak_hz_pinx leakage in the tristate pinx in hz state; forced 0 v < vpinx < vout; pinx = sdo ? 10 10 a ileak_od leakage of an open ? drain output open ? drain pinx in high state; forced vpinx = vout; pinx = intn, rstn, uvn_vout ? 10 10 a v_mid_digout_low v_mid value guaranteeing low level on rstn and uvn_vout pins shut ? down mode; rstn and uvn_vout connected to fixed 5 v through a 10 k resistor. if v_mid > v_mid_digout_low or vout > vout_digout_low , then rstn and uvn_vout stay below 400 mv not tested in production; guaranteed by design 1.9 v vout_digout_low vout value guaranteeing low level on rstn and uvn_vout pins 2.7 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 48 cfg and swdm pins table 37. electrical characteristics of cfg and swdm inputs symbol parameter conditions min typ max unit vinl_hv_pinx low ? level input threshold pinx = cfg, swdm 0 0.8 v vinh_hv_pinx high ? level input threshold 2 vs v rpulldown_hv_pinx internal pull ? down to gnd pinx = cfg, swdm 55 100 185 k fso pins table 38. fsox pin electrical characteristics symbol parameter conditions min typ max unit i_fsox_inactive fsox current in inactive state fsox inactive (no failure), or hz ? part of the fso2/3 pattern. 0 v < v(fsox) < 28 v ? 2 2 a v_fsox_active voltage drop at fsox when active fso1 active or low ? part of the fso2/3 pattern; i(fsox) = 5 ma 0.4 v wu pin table 39. wu pin electrical characteristics symbol parameter conditions min typ max unit vth_wu wu pin threshold 2 4 v vhys_wu wu pin threshold hysteresis 0.1 0.7 v t_wu_filt wu wakeup filter time 10 50 s ipu_wu pull ? up current on wu pin v(wu) = 4 v ? 11 ? 3 a ipd_wu pull ? down current on wu pin v(wu) = 2 v 3 11 a www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 49 package dimensions case 940ab ? 01 issue o dim min max millimeters e2 3.90 4.10 a 2.65 a1 --- 0.10 l 0.50 0.90 e 0.50 bsc c 0.23 0.32 h 0.25 0.75 b 0.18 0.36 d2 5.70 5.90 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at mmc. 4. dimension b shall be measured between 0.10 and 0.25 from the tip. 5. dimensions d and e1 do not include mold flash, protrusions or gate burrs. dimensions d and e1 shall be determined at datum h. 6. this chamfer feature is optional. if it is not present, a pin one identifier must be loacated within the indic- ated area. pin 1 reference d e1 0.10 seating plane 36x b e e detail a --- soldering footprint l l2 gauge detail a e/2 detail b a2 2.35 2.60 e1 7.50 bsc plane seating plane c x c h end view a m 0.25 b t top view side view a-b 0.20 c 118 19 36 a b d detail b 36x a1 a2 c c d2 e2 bottom view 36x d 10.30 bsc e 10.30 bsc m1 5 15 5.90 36x 1.06 36x 0.36 0.50 dimensions: millimeters pitch 4.10 10.76 1 0.25 c s s 4x h a x = a or b h note 6 m1 m 36x www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCV7471 http://onsemi.com 50 table 40. device ordering information part number description package type shipping ? NCV7471dq5r2g system basis chip with dual lin, hs ? can and 500 ma boost ? buck dcdc ssop36 ? ep green 1500 pcs / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intelle ctual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising ou t of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary ove r time. all operating parameters , including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCV7471/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative www.datasheet.net/ datasheet pdf - http://www..co.kr/

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